Prepare qcom-next based on tag 'Linux 6.19-rc5' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git #171
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Replace the hardcoded context ID mask (0xFF0) with GENMASK(11, 4) to improve readability and follow kernel bitfield conventions. Use FIELD_PREP and FIELD_GET instead of manual shifts for setting and extracting ctxid values. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ekansh Gupta <[email protected]>
…support Current FastRPC message context uses a 12-bit mask where the upper 8 bits represent the context ID from idr_alloc_cyclic and the lower 4 bits represent the PD type. This layout works for normal FastRPC calls but fails for polling mode because DSP expects a 16-bit context with an additional async mode bit. To enable polling mode support from DSP(DSP writes to poll memory), DSP expects a 16-bit context where the upper 8 bits are context ID, the lower 4 bits are PD type and the 5th bit from the end denotes async mode(not yet upstreamed). If this bit is set, DSP disables polling. With the current design, odd context IDs set this bit, causing DSP to skip poll memory updates. Update the context mask to ensure a hole which won't get populated, ensuring polling mode works as expected. This is not a bug and the change is added to support polling mode. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ekansh Gupta <[email protected]>
For any remote call to DSP, after sending an invocation message, fastRPC driver waits for glink response and during this time the CPU can go into low power modes. This adds latency to overall fastrpc call as CPU wakeup and scheduling latencies are included. Add polling mode support with which fastRPC driver will poll continuously on a memory after sending a message to remote subsystem which will eliminate CPU wakeup and scheduling latencies and reduce fastRPC overhead. Poll mode can be enabled by user by using FASTRPC_IOCTL_SET_OPTION ioctl request with FASTRPC_POLL_MODE request id. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ekansh Gupta <[email protected]>
…hy bindings for qcs8300 The gcc_aux_clk is not required by the PCIe PHY on qcs8300 and is not specified in the device tree node. Hence, move the qcs8300 phy compatibility entry into the list of PHYs that require six clocks. Removed the phy_aux clock from the PCIe PHY binding as it is no longer used by any instance. Link: https://lore.kernel.org/all/[email protected]/ Fixes: e46e59b ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2") Signed-off-by: Ziyue Zhang <[email protected]> Acked-by: Rob Herring (Arm) <[email protected]> Reviewed-by: Johan Hovold <[email protected]>
…en4 2-lanes PHY The fourth and sixth PCIe instances on Glymur are both Gen4 2-lane PHY. So document the compatible. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]>
Glymur platform has two Gen4 2-lanes controllers, the fourth and sixth instances. Add support for their PHYs. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Abel Vesa <[email protected]>
On the Qualcomm Glymur platform the PCIe host is compatible with the DWC controller present on the X1E80100 platform. So document the PCIe controllers found on Glymur and use the X1E80100 compatible string as a fallback in the schema. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Prudhvi Yarlagadda <[email protected]> Signed-off-by: Wenbin Yao <[email protected]> Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
Add a compatible for the Power Domain Controller on Kaanapali platforms. Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
…ali QMP PHY Document QMP combo PHY for Kaanapali. Use fallback to indicate the compatibility of the QMP PHY on the Kaanapali with that on the SM8750. Signed-off-by: Ronak Raheja <[email protected]> Co-developed-by: Jingyi Wang <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/linux-usb/[email protected]/
…Y for Kaanapali Document M31 eUSB2 PHY for Kaanapali which handles the USB2 path. Use fallback to indicate the compatibility of the M31 eUSB2 PHY on the Kaanapali with that on the SM8750. Signed-off-by: Ronak Raheja <[email protected]> Co-developed-by: Jingyi Wang <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/linux-usb/[email protected]/
… compatible Define a Glymur compatible string for the QMP combo PHY, along with resource requirements. Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
…atible The Glymur USB subsystem contains a multiport controller, which utilizes two QMP UNI PHYs. Add the proper compatible string for the Glymur SoC, and the required clkref clock name. Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Add the Glymur compatible to the M31 eUSB2 PHY, and use the SM8750 as the fallback. Signed-off-by: Wesley Cheng <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
…patible Add the compatible string for identifying a SMB2370 USB repeater device. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
…upport Introduce support for the SMB2370 based eUSB2 repeater. Configure the proper repeater tuning settings, as if this is not done correctly, it can lead to instability on the USB2 link, which leads to USB2 enumeration failures, or random disconnects. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Glymur contains a USB multiport controller which supports a QMP UNI PHY. These ports do not have typeC capability, so it needs to be differentiated in this manner. Update the QMP PHY sequence required to bring up the UNI PHY for Glymur. The UNI PHY follows mostly the same register field definitions as previous SoCs. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
QMP combo phy V6 and above use the clamp register from the PCS always on (AON) address space. Update the driver accordingly. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Elson Roy Serrao <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
For SuperSpeed USB to work properly, there is a set of HW settings that need to be programmed into the USB blocks within the QMP PHY. Ensure that these settings follow the latest settings mentioned in the HW programming guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some new ways to define certain registers, such as the replacement of TXA/RXA and TXB/RXB register sets. This was replaced with the LALB register set. There are also some PHY init updates to modify the PCS MISC register space. Without these, the QMP PHY PLL locking fails. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
…lymur platforms Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ for the same version number. So in order to be able to differentiate between them, add these ones with DP prefix. Add the necessary PHY setting tables for enabling the DP path within the QMP subsystem. Introduced some new callbacks for v8 specific sequences, such as for clock configurations based on the different link speeds. Wesley Cheng added some updated settings from the hardware programming guides on existing PHY tables and clock settings. Reviewed-by: Dmitry Baryshkov <[email protected]> Co-developed-by: Wesley Cheng <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Wesley Cheng <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Two platform-data fields for SM8750 were missed:
- get_vpu_buffer_size = iris_vpu33_buf_size
Without this, the driver fails to allocate the required internal
buffers, leading to basic decode/encode failures during session
bring-up.
- max_core_mbps = ((7680 * 4320) / 256) * 60
Without this capability exposed, capability checks are incomplete and
v4l2-compliance for encoder fails.
Link: https://lore.kernel.org/linux-media/[email protected]/
Fixes: a5925a2 ("media: iris: add VPU33 specific encoding buffer calculation")
Fixes: a688243 ("media: iris: Add support for ENUM_FRAMESIZES/FRAMEINTERVALS for encoder")
Cc: [email protected]
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dikshita Agarwal <[email protected]>
…e configuration The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform but has a different thermal junction temperature specification due to package-level differences. Update passive/hot trip thresholds to 105°C and critical trip thresholds to 115°C for various subsystem TSENS sensors. Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation is handled automatically in hardware on this board. Signed-off-by: Manaf Meethalavalappu Pallikunhi <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Most modern Qualcomm platforms (>= SM8150) expose information about the DDR memory present on the system via SMEM. Details from this information is used in various scenarios, such as multimedia drivers configuring the hardware based on the "Highest Bank address Bit" (hbb), or the list of valid frequencies in validation scenarios... Add support for parsing v3-v5 version of the structs. Unforunately, they are not versioned, so some elbow grease is necessary to determine which one is present. See for reference: v3: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/1d11897d2cfcc7b85f28ff74c445018dbbecac7a v4: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/f6e9aa549260bbc0bdcb156c2b05f48dc5963203 v5: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/blob/uefi.lnx.4.0.r31-rel/QcomModulePkg/Include/Protocol/DDRDetails.h?ref_type=heads Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Vishnu Santhosh <[email protected]>
Add the camera DT binding header, which will be utilized by the camera downstream drivers and DTSI files. Signed-off-by: Chandan Kumar Jha <[email protected]>
Add CAMX overlay dts file for lemans boards. This change also enables the compilation of the CAMX overlay on Lemans boards. Co-developed-by: Vikram Sharma <[email protected]> Signed-off-by: Vikram Sharma <[email protected]> Signed-off-by: Chandan Kumar Jha <[email protected]>
Add CAMX overlay dts file for rb3gen2 vision mezzanine board. This change also enables the compilation of the CAMX overlay for Kodiak rb3gen2 vision mezzanine board. Signed-off-by: Chandan Kumar Jha <[email protected]>
Add CAMX overlay dts file for Monaco boards. This change also enables the compilation of the CAMX overlay for Monaco boards. Signed-off-by: Chandan Kumar Jha <[email protected]>
The camera firmware size for IoT variant qcs8300 SoC is more than 5MB. Update the PIL memory region size of camera to 7MB to accomodate the same. Signed-off-by: Umang Chheda <[email protected]>
- Fix the indentation issue. Signed-off-by: Chandan Kumar Jha <[email protected]>
- Fix the indentation issue. - Update DT clock property name after clock. - Short DT nodes. - Fix indexing issue. - Update gpios shared pin. Signed-off-by: Chandan Kumar Jha <[email protected]>
- Fix the indentation issue. - Update DT clock property name after clock. - Shorted DT nodes. Signed-off-by: Chandan Kumar Jha <[email protected]>
# Conflicts: # Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # arch/arm64/boot/dts/qcom/talos.dtsi
# Conflicts: # include/linux/firmware/qcom/qcom_scm.h
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <[email protected]>
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Name SHA Commits
tech/bsp/clk 567d776 19
tech/security/firmware-smc a50984a 2
tech/bsp/soc-infra 2949741 9
tech/bsp/remoteproc 27311a4 15
tech/bus/peripherals 486bcf7 1
tech/bus/pci/all 2fdd372 9
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy 9e7d778 13
tech/debug/hwtracing 88c50d8 27
tech/pmic/misc 91e88b9 16
tech/pmic/regulator 81fc8fb 6
tech/mem/iommu 486a41c 2
tech/mm/audio/all ce10fd3 4
tech/mm/camss d1d2c38 3
tech/mm/drm 9bb86be 28
tech/mm/fastrpc 844e24f 4
tech/mm/video 4871417 16
tech/mm/gpu 1651b6d 5
tech/mproc/rpmsg c3875d9 1
tech/net/ath dd2aee0 20
tech/net/eth c280d7e 1
tech/net/bluetooth ee968c9 3
tech/pm/power 7b7e779 7
tech/pm/thermal 363f414 3
tech/security/crypto fa6b06a 11
tech/storage/all ba8c93d 6
tech/all/dt/qcs6490 87b5b8c 7
tech/all/dt/qcs9100 d8bc255 14
tech/all/dt/qcs8300 03de422 27
tech/all/dt/qcs615 648a531 11
tech/all/dt/hamoa 4c89453 11
tech/all/dt/glymur b6ddb1f 27
tech/all/dt/kaanapali 15ce26e 6
tech/all/dt/pakala b4ebc9f 9
tech/all/config d2f2062 35
tech/overlay/dt 50f2b36 15
tech/all/workaround ec47ebe 3
tech/mproc/all d19a4c1 5
tech/noup/debug/all 1c86d19 5