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@openroad-ci openroad-ci commented Jan 19, 2026

Between the canonicalization step and the rest of synthesis we store a .rtlil checkpoint. Make it smaller by stripping standard cell definitions from it.

Resolves #3815

Updated Rules

[WARNING] Multiple clocks not supported. Will use first clock: mrx_clk_pad_i: 300.0000.
[WARNING] Multiple clocks not supported. Will use first clock: mrx_clk_pad_i: 300.0000.
designs/asap7/jpeg_lvt/rules-base.json updates:

Metric Old New Type
globalroute__timing__setup__tns -120.0 -277.0 Failing

designs/asap7/mock-alu/rules-base.json updates:

Metric Old New Type
cts__timing__setup__ws -278.0 -310.0 Failing
globalroute__timing__setup__ws -295.0 -320.0 Failing
finish__timing__setup__ws -271.0 -306.0 Failing
finish__timing__setup__tns -17200.0 -17500.0 Failing

[WARNING] Multiple clocks not supported. Will use first clock: clk: 333.0000.
designs/asap7/uart/rules-base.json updates:

Metric Old New Type
cts__timing__setup__ws -36.3 -55.2 Failing
cts__timing__setup__tns -783.0 -1920.0 Failing
globalroute__timing__setup__ws -48.7 -64.4 Failing
globalroute__timing__setup__tns -1510.0 -2680.0 Failing
finish__timing__setup__ws -37.8 -54.0 Failing
finish__timing__setup__tns -840.0 -1860.0 Failing

designs/nangate45/bp_be_top/rules-base.json updates:

Metric Old New Type
cts__timing__setup__tns -19.8 -26.0 Failing
globalroute__timing__setup__tns -23.8 -31.0 Failing
finish__timing__setup__tns -24.4 -29.1 Failing

designs/nangate45/ibex/rules-base.json updates:

Metric Old New Type
globalroute__timing__setup__tns -0.443 -1.69 Failing

designs/nangate45/jpeg/rules-base.json updates:

Metric Old New Type
cts__timing__setup__tns -36.4 -37.0 Failing

[WARNING] Multiple clocks not supported. Will use first clock: clk_i: 3.0000.
designs/sky130hd/jpeg/rules-base.json updates:

Metric Old New Type
globalroute__antenna_diodes_count 102 163 Failing

[WARNING] Multiple clocks not supported. Will use first clock: ext_clk: 15.0000.
designs/sky130hd/microwatt/rules-base.json updates:

Metric Old New Type
detailedroute__antenna__violating__nets 0 1 Failing

designs/sky130hs/ibex/rules-base.json updates:

Metric Old New Type
cts__timing__setup__tns -1.42 -2.9 Failing
globalroute__timing__setup__tns -54.1 -140.0 Failing
finish__timing__setup__tns -2.86 -33.4 Failing

designs/sky130hs/riscv32i/rules-base.json updates:

Metric Old New Type
globalroute__timing__setup__tns -10.1 -11.1 Failing

Messages from CI

[INFO] asap7/minimal not included in CI.
[INFO] gf12 not included in the update.
[INFO] gf55 not included in the update.
[INFO] nangate45/bp_quad not included in CI.
[INFO] rapidus2hp not included in the update.

Between the canonicalization step and the rest of synthesis we store
a .rtlil checkpoint. Make it smaller by stripping standard cell
definitions from it.

Signed-off-by: Martin Povišer <povik@cutebit.org>
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povik commented Jan 19, 2026

@oharboe take two, we'll see if any errors appear

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oharboe commented Jan 19, 2026

@povik I suppose the difference in WNS is just the garden variety Yosys churn?

13:31:13  [ERROR] finish__timing__setup__tns fail test: -31.9901 >= -2.86

@povik povik added the UpdateRules Starts GHA to update rules label Jan 19, 2026
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povik commented Jan 19, 2026

@oharboe I think so, yeah

Signed-off-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
@openroad-ci openroad-ci removed the UpdateRules Starts GHA to update rules label Jan 19, 2026
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oharboe commented Jan 19, 2026

@oharboe I think so, yeah

🤞

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oharboe commented Jan 21, 2026

@maliberty Thoughts?

Comment on lines +16 to +17
# Strip away standard cell definitions to make the checkpoint smaller.
delete =A:\liberty_cell=1
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@povik you'll have a better idea than I do if this is a good change.

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I think it's fine even though it relies on undocumented yosys behavior. We can always go back

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Why does this change QOR?

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povik commented Jan 21, 2026

I think the ball is in my court to resolve the conflict and add update of private metrics. I had a secure CI running but before I reacted to its results the public metrics went stale

Why does this change QOR?

The theory is internal yosys counters used for naming objects are influenced by the extra read_liberty command. This propagates to different iteration order and optimization results

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oharboe commented Jan 23, 2026

merge?

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It has conflicts so no

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Scrub liberty cells from canonicalized .rtlil in synthesis

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