Skip to content

feat(SRAM): use ValName for better and steady naming #84

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
Tang-Haojin wants to merge 1 commit into
base: master
Choose a base branch
from
Open

feat(SRAM): use ValName for better and steady naming #84

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 8 additions & 5 deletions src/main/scala/utility/SRAMTemplate.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@ package utility

import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.ValName

class SRAMBundleA(val set: Int) extends Bundle {
val setIdx = Output(UInt(log2Up(set).W))
Expand Down Expand Up @@ -140,7 +141,7 @@ class SRAMTemplate[T <: Data](
shouldReset: Boolean = false, extraReset: Boolean = false,
holdRead: Boolean = false, bypassWrite: Boolean = false,
useBitmask: Boolean = false,
) extends Module {
)(implicit valName: ValName) extends Module {
val io = IO(new Bundle {
val r = Flipped(new SRAMReadBus(gen, set, way))
val w = Flipped(new SRAMWriteBus(gen, set, way, useBitmask))
Expand All @@ -151,7 +152,7 @@ class SRAMTemplate[T <: Data](
val arrayWidth = if (useBitmask) 1 else gen.getWidth
val arrayType = UInt(arrayWidth.W)
val arrayPortSize = if (useBitmask) way * gen.getWidth else way
val array = SyncReadMem(set, Vec(arrayPortSize, arrayType))
val array = SyncReadMem(set, Vec(arrayPortSize, arrayType)).suggestName(valName.name)
val (resetState, resetSet) = (WireInit(false.B), WireInit(0.U))

if (shouldReset) {
Expand Down Expand Up @@ -229,7 +230,7 @@ class FoldedSRAMTemplate[T <: Data](
shouldReset: Boolean = false, extraReset: Boolean = false,
holdRead: Boolean = false, singlePort: Boolean = false,
bypassWrite: Boolean = false, useBitmask: Boolean = false,
) extends Module {
)(implicit valName: ValName) extends Module {
val io = IO(new Bundle {
val r = Flipped(new SRAMReadBus(gen, set, way))
val w = Flipped(new SRAMWriteBus(gen, set, way, useBitmask))
Expand Down Expand Up @@ -286,8 +287,10 @@ class FoldedSRAMTemplate[T <: Data](
array.io.w.apply(wen, wdata, waddr, wmask)
}
}
class SRAMTemplateWithArbiter[T <: Data](nRead: Int, gen: T, set: Int, way: Int = 1,
shouldReset: Boolean = false) extends Module {
class SRAMTemplateWithArbiter[T <: Data](
nRead: Int, gen: T, set: Int, way: Int = 1,
shouldReset: Boolean = false
)(implicit valName: ValName) extends Module {
val io = IO(new Bundle {
val r = Flipped(Vec(nRead, new SRAMReadBus(gen, set, way)))
val w = Flipped(new SRAMWriteBus(gen, set, way))
Expand Down